IBM did a technology trade-off in the Power2+ designed to leverage
the Power2's architecture in order to reach new markets. "The primary
project goals we had for the Power2+ project were that we really wanted
to leverage off the original Power2 design and really went after two
main areas, the first one being targeted transaction commercial processing.
And the second was that we wanted to push the Power2 technology down
to a lowercost, desktop-type machine," said David Shippy, an executive
from IBM's RISC Systems/6000 Division, at Hot Chips.
In order to address these two markets with the Power2+, IBM reduced
the data cache by half and the memory word interface from 8-word size
to 4-word. The result is that performance is increased in low-end
systems such as the RISC System/6000 (RS/6000) desktop computer system
model 390, with a Power2+ chipset. The Power2+ model 390 features
67MHz clock operation and boasts SPECfp92 rating of 205.3; compared
to the model 380 with a Power2 processor, that operates at clock speed
of 59MHz and has a lower SPECfp92 rating of 187.2.
At the high-end, however, the Power2+ in the RS/6000 model R24 system
operates at the same 71.5MHz clock speed as the Power2 in the model
990; and in terms of performance the model R24 actually drops behind
the model 990 in SPECfp92 rating, with the model R24 system posting
a SPECfp92 rating of 273.8 while the model 990 system reaches a slightly
higher SPECfp92 rating of 279.
In the area of transaction processing, however, the Power2+ systems
shine. In the model R24, the transactionsper-second rating (tpsA)
is 357.2, nearly 80 basis points higher than the 275.6 tpsA rating
in the model 990. This gives IBM just what it wanted--albeit achieved
by performance tradeoffs--a chip suitable for both low-end PCs and
high-end transaction processing systems. The device offers "the highest
transaction processing performance level for any processor that's
out there today," according to Mr. Shippy.
The Power2+ is manufactured using 0.7-micron process, four levels
of metal and a level of polysilicon. The technology comes in a ceramic
multichip module (MCM) package which includes four data cache chips,
and a single solder balll connect (SBC) package for a cost-reduced
chipset which includes two data cache units.
In terms of future developments, Mr. Shippy noted, "What you'll
see with future technology is more of the core CPU--fixed point unit,
floating point unit, will all be integrated onto a single chip and
that'll help improve performance there, and the multichip module will
help us package other high-speed interfaces onto the chip so it will
scale to get to the really high-end performance."
Meanwhile, DEC unveiled its Alpha AXP 21164 successor to the 21064
anticipated since earlier this year (EN, April 25). The AXP 21164
is manufactured using 0.4-micron process and achieves 300MHz typical
operating speed while using between 40 and 50 watts power. In order
to overcome possible heat problems, "the device features a detachable
heat sink that can even cool it in PC-type environments," according
to Paul Rubinfeld of
DEC's Hudson, Mass, Semiconductor Engineering Group.
The AXP 21164 is a new design of the Alpha processor that features
quad instruction issue, on-chip secondary cache and the ability to
achieve a short latency at a high clock speed. In terms of enhancements
over the previous generation 21064, the 21164 offers reduced key latencies
such as wider integer multiply--a range of 19-23 compared to 8-16
for the 21064--four floating point cycles for the 21164 compared to
six for the 21064, and two L1 data cache cycles compared to three
cycles for the 21064.
DEC's new processor features performance specmarks of better than
1 SPECint92 per MHz, better than 1.5 SPECfp92 per MHz and better than
2 transactions-per-second per MHz, Mr. Rubinfeld said. Key features
include 4-way issue superscalar architecture, on-chip L2 cache that
provides at least three 32-byte blocks ahead of the current issue
point, 7-stage integer pipeline, 9-stage floating point pipeline,
emphasis on low latency at high clock rate and high throughput memory
Other microprocessor developments at the symposium included other
chip vendors offering additional insights into their most recent devices,
such as Metaflow Technologies' 50MHz "Thunder" version of the Lightning
SPARC chipset design--with 80MHz and 120Mhz versions on the way, and
NEC's experimental 500MHz "Gallop" RISC processor--first discussed
at the 1994 IEEE International Solid State Circuits Conference (ISSCC)
in San Francisco earlier this year (EN, Feb. 21).
NEC recapped its Gallop 500MHz, 32-bit CMOS RISC processor first
presented at ISSCC in February. The Gallop chip is an experimental
design that features 0.4-micron CMOS 3-level aluminum design incorporating
201,478 transistors on a 7.9mm x 8.84mm chip. It uses a single 3.3-
volt power supply and has a power dissipation rate of 6 watts at 500MHz.
"We had to solve several problems that the architecture and circuit
design faced," said Kazumasa Suzuki of NEC's System ULSI Research
Lab. Among the challenges were integrating high speed function blocks,
and increasing speed while keeping voltage low. "The voltage load
of the power supply makes the operation speed slow, and the noise
caused by the chip operation resulted in errors." In order to overcome
such problems, NEC has developed several techniques for increasing
the speed of the MPU. Among the techniques: use of NEC's 3-level metal
0.4-micron process, as well as "development of high speed function
blocks, design of a high-speed microprocessor architecture and integration
techniques for the high-speed function blocks."
The Gallop chip architecture features 8-stage pipelined datapath,
with simple datapath control--no pipeline hold and no register forearding,
and on-chip test functions. High-speed circuit techniques include
power and ground line structures that include up to 240 power lines,
stageconnect clock distribution, high-speed input and output buffer
circuit, and high-frequency PLL (phase locked loop) clockgenerator.
Bruce D. Lightner, co-founder and VP of development at Metaflow,
a La Jolla, Calif. Design company, said the 50MHz Thunder SPARC processor
is a new implementation of the 4-chip "Lightning" SPARC chipset that
Metaflow developed for LSI Logic (completed in 1991 but never introduced).
The Thunder project was 100 percent funded by Hyundai Electronics,
a co-founder of Metaflow.
The 5-volt device incorporates 6 million transistors and features
a patented out-of-order execution architecture that is said to eliminate
processor stalls. Thunder consists of four chips: the integer unit,
cache control/MMU/Bus Interface (CMB), Xcache RAM (1MB), and floating
Thunder is currently being manufactured by VLSI Technologies in
a 391-pin IPGA package using both 0.6- and 0.8-micron process. In
4Q94, Metaflow will roll out a 80MHz version in a 600+ TBGA package,
fabricated on 0.5-micron process. A 120MHz version, also on 0.5M
process, is planned for 1995.
Mr. Lightner hinted at a foundry change by stating "I can't talk
about our foundry partner today" for the planned 80MHz and 120MHz
versions. In terms of performance goals, he said, "by the end of the
year, we will achieve almost 200 SPECints and 400 SPECfp."
VADEM WINS BELLSOUTH DESIGN-IN
ORLANDO, FLA.--BellSouth last week announced availability of its
"Simon" smart cellular phone that was designed by IBM and incorporates
Vadem's VG-230 processor. When introducing Simon last year (EN, Nov.
8, 1993), BellSouth had not revealed the Vadem design-in.
The VG-230 is a 16MHz DOS-engine built around NEC's V30 CPU. Earlier
this year, Vadem, San Jose, Calif., said it would upgrade its VG-230
to higher speeds; however, BellSouth is using the 16MHz device. Vadem
won a big design-in with Sharp Electronics last year for the PT-9000
personal digital assistant. The V30 core is compatible with Intel'
s 8086 microprocessor.
BellSouth said its Simon communicator has a pen for digital input,
a PCMCIA slot, a 9.6K bit/sec. fax/modem and a series of menus for
address books and phone numbers. It is priced at about $900.
COPYRIGHT 1994 Cahners Publishing Company
DeTar, Jim, IBM details Power2+; DEC bares new Alpha AXP. (Alpha AXP 21164 microprocessor) (Product Announcement)., Vol. 40, Electronic News, 08-22-1994, pp 2(2).